1. Field of the Invention
The present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to a method of increasing the performance of memory cell devices, such as SRAM memory devices, by performing a unique ion implantation scheme.
2. Description of the Related Art
Semiconductor memory devices are in widespread use in many modern integrated circuit devices and in many consumer products. In general, memory devices are the means by which electrical information is stored. There are many types of memory devices, SRAMs (Static Random Access Memory), DRAMs (Dynamic Random Access Memory), ROMs (Read Only Memory), etc., each of which has its own advantages and disadvantages relative to other types of memory devices. For example, SRAMs are typically employed in applications where higher speed and/or reduced power consumption is important, e.g., cache memory of a microprocessor, mobile phones and other mobile consumer products, etc. Millions of such memory devices are typically included in even very basic electronic consumer products. Irrespective of the type of memory device, there is a constant drive in the industry to increase the performance and durability of such memory devices. In typical operations, an electrical charge (HIGH) is stored in the memory device to represent a digital “1”, while the absence of such an electrical charge or a relatively low charge (LOW) stored in the device indicates a digital “0”. Special read/write circuitry is used to access the memory device to store digital information on such a memory device and to determine whether or not a charge is presently stored in the memory device. These program/erase cycles (“P/E cycles”) typically occur millions of times for a single memory device over its effective lifetime.
In general, efforts have been made to reduce the physical size of such memory devices, particularly reducing the physical size of components of the memory devices, such as transistors, to increase the density of memory devices, thereby increasing performance and decreasing the costs of the integrated circuits incorporating such memory devices. Increases in the density of the memory devices may be accomplished by forming smaller structures within the memory device and by reducing the separation between the memory devices and/or between the structures that make up the memory device. Often, these smaller design rules are accompanied by layout, design and architectural modifications which are either made possible by the reduced sizes of the memory device or its components, or such modifications are necessary to maintain performance when such smaller design rules are implemented. As an example, the reduced operating voltages used in many modern-day conventional integrated circuits are made possible by improvements in design, such as reduced gate insulation thicknesses in the component transistors and improved tolerance controls in lithographic processing. On the other hand, reduced design rules make reduced operating voltages essential to limit the effects of hot carriers generated in small size devices operating at higher, previously conventional operating voltages.
Making SRAMs in accordance with smaller design rules, as well as using reduced internal operating voltages, can reduce the stability of SRAM cells. Reduced operating voltages and other design changes can reduce the voltage margins which ensure that an SRAM cell remains in a stable data state during a data read operation, increasing the likelihood that the read operation could render indeterminate or lose entirely the data stored in the SRAM cell. As shown in FIG. 1, a typical 6T (six transistors) SRAM memory cell 200 includes two NMOS pass gate transistors 102A/B, two PMOS pull-up transistors 104A/B, and two NMOS pull-down transistors 106A/B. Each of the PMOS pull-up transistors 104A/B has its gate connected to the gate of a corresponding NMOS pull-down transistor 106A/B. The drains of the PMOS pull-up transistors 104A/B have their drains connected to the drains of corresponding NMOS pull-down transistors 106A/B to form inverters having the conventional configuration. The sources of the PMOS pull-up transistors 104A/B are connected to a high reference potential, typically VCC, and the sources of the NMOS pull-down transistors 106A/B are connected to a lower reference potential, typically VSS or ground. The gates of the PMOS pull-up transistor 104A and the NMOS pull-down transistor 106A, which make up one inverter, are connected to the drains of the transistors 104B, 106B of the other inverter. Similarly, the gates of the PMOS pull-up transistor 104B and the NMOS pull-down transistor 106B, which make up the other inverter, are connected to the drains of the transistors 104A, 106A. Hence, the potential present on the drains of the transistors 104A, 106A (node N1) of the first inverter is applied to the gates of transistors 104B, 106B of the second inverter and the charge serves to keep the second inverter in an ON or OFF state. The logically opposite potential is present on the drains of the transistors 104B, 106B (node N2) of the second inverter and on the gates of the transistors 104A, 106A of the first inverter, keeping the first inverter in the complementary OFF or ON state relative to the second inverter. Thus, the latch of the illustrated SRAM cell 200 has two stable states: a first state with a predefined potential present on charge storage node N1 and a low potential on charge storage node N2; and a second state with a low potential on charge storage node N1 and the predefined potential on charge storage node N2. Binary data are recorded by toggling between the two states of the latch. Sufficient charge must be stored on the charge storage node, and thus on the coupled gates of associated inverter, to unambiguously hold one of the inverters “ON” and unambiguously hold the other of the inverters “OFF”, thereby preserving the memory state. The stability of an SRAM cell 200 can be quantified by the margin by which the potential on the charge storage nodes can vary from its nominal value while still keeping the SRAM 200 cell in its original state.
Data is read out of the conventional SRAM cell 200 in a non-destructive manner by selectively coupling each charge storage node (N1, N2) to a corresponding one of a pair of complementary bit lines (BL, BL). The selective coupling is accomplished by the aforementioned of pass gate transistors 102A/B, where each pass gate transistor is connected between one of the charge storage nodes (N1, N2) and one of the complementary bit lines (BL, BL). Word line signals are provided to the gates of the pass gate transistors 102A/B to switch the pass gate transistors ON during data read operations. Charge flows through the ON pass gate transistors to or from the charge storage nodes (N1, N2), discharging one of the bit lines and charging the other of the bit lines. The voltage changes on the bit lines are sensed by a differential amplifier (not shown).
Prior to a read out operation, the bit lines BL, BL are typically equalized at a voltage midway between the high and low reference voltages, typically ½ (VCC-VSS), and then a signal on the word line WL turns the pass gate transistors 102A/B ON. As an example, consider that N1 is charged to a predetermined potential of VCC and N2 is charged to a lower potential VSS. When the pass gate transistors 102A/B turn ON, charge begins flowing from node N1 through pass gate transistor 102A to bit line BL. The charge on node N1 begins to drain off to the bit line BL and is replenished by charge flowing through pull-up transistor 104A to node N1. At the same time, charge flows from bit line BL through pass gate transistor 102B to node N2 and the charge flows from the node N2 through the pull-down transistor 106B. To the extent that more current flows through pass gate transistor 102A than flows through pull-up transistor 104A, charge begins to drain from the node N1, which, on diminishing to a certain level, can begin turning OFF pull-down transistor 106B. To the extent that more current flows through pass transistor 102B than flows through pull-down transistor 106B, charge begins to accumulate on charge storage node N2, which, on charging to a certain level, can begin turning OFF pull-up transistor 104A.
For the SRAM cell's latch to remain stable during such a data reading operation, at least one of the charge storage nodes (N1, N2) within the SRAM cell 200 must charge or discharge at a faster rate than charge flows from or to the corresponding bit line. In the past, one technique used to achieve this control is to configure the various transistors of the cell 200 such that the pass gate transistors 102A/B are strong enough to over-write the pull-up transistors 104A/B during a write operation, but weak enough so as to not over-write the pull-down transistors 106A/B during a read operation. One way this has been accomplished is to insure that the gate width of the pass transistors 102A/B is less than the gate width of the pull-down transistors 106A/B, but wider than the gate width of the pull-up transistors 104A/B. For very scaled memory cells, this difference in the gate widths of the various transistors may not provide enough confidence that the memory cell 200 will remain stable during operation. Another technique that has been employed, in addition to the difference in gate widths, is to provide an additional well implant (P-type dopant) for the pass gate transistors 102A/B in an attempt to further insure that the threshold voltage (Vt) of the pass gate transistors 102A/B is sufficiently high so as not to flip the bit cell during a read operation. This additional pass gate transistor well implant requires one additional masking operation and it tends to result in higher channel doping for the pass gate transistors 102A/B as compared to the pull-down transistors 106A/B, which has the desired effect of decreasing the performance of the pass gate transistors 102A/B as compared to the pull-down transistors 106A/B. However, this additional pass gate transistor well implant does have some adverse consequences as well, like higher gate induced leakage currents and greater variability due to more random dopant concentrations in the pass gate transistors 102A/B. Additionally, in highly scaled devices, due to manufacturing errors, e.g., undesirable dopant diffusion, misalignment of masking layers used during the implantation process, etc., the pull-down transistors 106A/B may also be affected by the additional pass gate transistor well implant process.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.